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authordakkar <dakkar@thenautilus.net>2022-03-25 11:54:06 +0000
committerdakkar <dakkar@thenautilus.net>2022-03-25 11:54:06 +0000
commit7af304e9c5b3b1ed12920ad29025a707d5821f6d (patch)
treeb92927b903d3a0e6803bab9a7b8fdeb4884edd53
parentholes in the middle layer (diff)
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better placement of cable hole
-rw-r--r--enclosure/enclosure.scad5
1 files changed, 3 insertions, 2 deletions
diff --git a/enclosure/enclosure.scad b/enclosure/enclosure.scad
index 0873127..bb32696 100644
--- a/enclosure/enclosure.scad
+++ b/enclosure/enclosure.scad
@@ -32,7 +32,7 @@ CO_Z=8;
CO_CONN_Y=10;
BOT_CABLE_WELL_X=25; // just some space for the battery & pm cables
-CABLE_HOLE_DIAM=10;
+CABLE_HOLE_DIAM=12.5;
BOTTOM_Z=WALL_THICKNESS + PM_Z;
MIDDLE_Z=WALL_THICKNESS + CO_Z;
@@ -246,6 +246,7 @@ module bottom() {
module middle() {
CABLE_HOLE_X_OFF= TOTAL_X/2 - PM_X - BOT_CABLE_WELL_X/2;
+ CABLE_HOLE_Y_OFF= -PM_Y/2 + PM_CONN_Y/2;
CO_X_OFF=(TOTAL_X - CO_X)/2 - WALL_THICKNESS;
CO_Z_OFF=MIDDLE_Z - CO_Z;
@@ -256,7 +257,7 @@ module middle() {
difference() {
box([TOTAL_X, TOTAL_Y, MIDDLE_Z]);
screw_holes();
- translate([CABLE_HOLE_X_OFF, 0, 0]) cable_hole();
+ translate([CABLE_HOLE_X_OFF, CABLE_HOLE_Y_OFF, 0]) cable_hole();
translate([CO_X_OFF, 0, CO_Z_OFF]) co_sensor();
translate([0, 0, CO_Z_OFF]) middle_cable_well();
translate([0,0, CO_Z_OFF]) board_well();